Verilog, System Verilog, RTL Coding, Full Chip Integration, System Verilog assertions, scripting in Perl

static timing analysis, LINT, Logic Synthesis, Dft, cdc, formal verification, Cadence-based ASIC design environments, low-power design methodologies, micro-architecture development, SystemVerilog RTL design

Servicenow, Soap, Uipath, Rpa, Scripting, Automation Anywhere, Orchestration, REST, Technical Troubleshooting, Analytical Skills, Flow Designer, ServiceNow RPA Hub, AI agents, platform architecture, Problem-solving, ServiceNow data model, IntegrationHub, bots, SaaS-based automation systems

static timing analysis, Dft, low-power design methodologies, LINT, Cadence-based ASIC design environments, micro-architecture development, SystemVerilog RTL design, formal verification, Logic Synthesis, cdc

Static Timing Analysis (STA), Advanced STA methodologies, Chip design flow, 3DIC stacking and packaging, Standard cell/MEM/IO IP library modeling, ECO and power optimization flows

Scripting, Floor-Planning, AI tools, Cadence, RTL2GDS flow, Chip Finishing, flow automation, Physical Verification, Synthesis, Physical Design, Power Distribution, Metal Dummy Fill, Synopsys, Place And Route, Clock Tree Synthesis