Usb, Fpga, Perl, Pcie, Python, verification methodologies, coverage driven verification, Emulation, directed constrained-random tests, Uvm, systemverilog, formal verification, MIPI, AMBA, Test Bench, transaction level modeling, AXI4

arm architecture , Git, Gerrit, Embedded C Programming, Bare-metal programming, Boot-time software, Embedded Systems, SoC subsystems

Debugging Tools, Pcie, Ethernet, DSP algorithms, clock validation, memory subsystems, fuse controllers, verification methodologies, Simulation Tools, AMBA protocols, IP Subsystem SoC-level verification, microarchitecture concepts, systemverilog, coverage closure, boot flows, security validation flows, random test case development, debugging capabilities for SoC fabric, advanced computer architecture, Performance Analysis

code coverage , perl, C, Regression Testing, Ovm, Pcie, Ethernet, Python, Uvm, systemverilog, Axi, DDR protocols, RTL simulators, X-propagation, functional coverage

DDR, Usb, C, Pcie, Uart, I2c, Spi, Object-Oriented Programming, I3C, Uvm, systemverilog

Fpga, Algorithm Development, VLSI CAD software, Statistical Techniques, VLSI architecture, RTL design using Verilog, systemverilog, Xilinx Vivado

Cache, Soc Architecture, Verilog, power analysis, Synthesis, memory compression, FPGA design verification, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, FPGA and emulation platforms, Dft, fabric coherence, low-power design techniques, assertion-based formal verification