C, Pcie, Perl, Python, Tcl, UFS, HSIO PHY Controllers, Skill, Open Verification Methodology, USB2, systemverilog, MIPI, USB3, Universal Verification Methodology

Debuggers, power-saving mechanisms, trend detection, Data Analysis, tester-to-system correlation, DMM, DAQ, Oscilloscopes, power characterization, metric extraction, AI-enabled workflows

Usb, Fpga, Pcie, Perl, Python, verification methodologies, Emulation, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, MIPI, formal verification, AMBA, Test Bench, transaction level modeling, AXI4

Verilog, System Verilog, AI-powered tools, Timing Closure, EDA design processes, ASIC Design, Simulation and debugging, Functional verification tools, Synthesis tools

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

power converters , post layout parasitic extraction, Monte Carlo analysis, bandgaps, sensing circuitry, Simulation, block level topology selection, Spectre, switching regulators, schematic generation, DACs, VHDL, charge pumps, Amplifiers, physical layout management, Spice, Transistor Level Design, Comparators, IC CAD tools, analog and mixed signal design, precision analog control