C, Scripting Languages, Gdb, Verilog, Python, Indago, Micro-Architecture, ASIC Architecture, SOC design, Cadence, Verification, Physical Design, Timing Closure, Rtl Design

Integration, C, Gdb, Verilog, Scripting Languages, Python, Synthesis, RTL Build, Indago, Micro-Architecture, Cadence, SOC design, Physical Design, Rtl Design, Dft, Design Automation, Timing Closure, Verification, ASIC architecture

Usb, Jtag, Pcie, Perl, Ethernet, Python, System Verilog, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB

Computer Architecture, reset methodologies, Timing Constraints, Microarchitecture, digital RTL design