Unix, C, Systemc, Debugging, Linux, Makefile, Verilog, System Verilog, Perforce, Python, Perl, Shell Programming, Computer Architecture, Simulation, Uvm, ASIC design process, coverage closure, CVS, UVM-based design verification methodologies, test bench development, Design Verification tools, Digital Design

systemverilog, Uvm, Register modeling, PHY architectures, Regression management, coverage analysis, SERDES, Firmware interaction

Python, Tcl, Analog mixed-signal IC design, behavioral modeling, systemverilog, Spectre, Rtl Design, Verification methodologies, Mixed-signal simulation tools, Verilog-AMS, AMS Designer, Cadence Virtuoso