bist , C, Vcs, Verilog, Python, Asic verification, Genus Design Compiler, digital timing constraints, XCelium, high-speed SerDes, SOC interconnect fabrics, ASIC tool flows, Scan Insertion, DFT methodologies, Timing Analysis, systemverilog, FPGAs, ASIC synthesis, Questa tools, Axi, AMBA, Timing Constraints, ATPG, APB, microcontroller platforms, Cadence Virtuoso, AHB

DAST, Penetration Testing, Mac, Burp Suite, Linux, Web Application Security Testing, Nmap, Windows, Python, Golang, Nuclei

System Verilog, Axi, dv methodologies and tools, Bus protocols like AHB, ACE-Lite, Ace, Digital design concepts, LPDDR5 protocols, Debug, Uvm

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug

Unix, FTP, C, Ant, Apache Tomcat, Groovy, Javascript, Docker, Oracle, Python, AWS, Java, Solaris, Grails, Ssh, Jboss, Shell Scripting, J2EE, SSL, Jenkins, Weblogic, Perl, Linux, Ansible, Zookeeper, Gitlab, Pgp, Puppet, Kubernetes, CVS, Chef, Consul, Fabric

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development cycle, systemverilog, Rtl Design, spyglass, EVE, Veloce, ASIC Design, formal verification