Ovm, Verilog, System Verilog, DFI protocol, formal verification, Jedec standards, Functional Verification Coverage, Design Verification, Uvm, Low Power Verification, Gate Simulation

Jtag, Perl, Verilog, Python, System Verilog, Tcl, Mentor Questa, Cadence Xcelium, JasperGold, Uvm, Synopsys VCS, APB, EDA Tools, CRI, IJTAG

System Verilog, Data path verification performance tests, Building test benches from scratch, Gate level simulation, ASIC verification using UVM

Python Scripting, Jasper, Verilog, System Verilog, formal verification, VC-FORMAL, SVA

Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

Usb, Jtag, Perl, Pcie, Ethernet, System Verilog, Python, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB

Jasper, Python Scripting, Verilog, System Verilog, formal verification, VC-FORMAL, SVA