power optimization , Perl, Scripting, Python, Tcl, Cadence, Mentor, Timing Analysis, Physical Design, Signal Integrity, EDA Tools, Synopsys

redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

routing, block level place and route, floor-planning, Power grid analysis, Extraction, Physical Synthesis, Netlist, full chip implementation, GDS flow, STA timing, flow-automation, Signal Integrity, clock tree optimization, formal verification, Dft, Timing Constraints, Regression, digital design automation, Timing Closure, CTS IO timing, RTL-to-GDSII, Antenna fixing

Physical Design CAD

Physical Design CAD

Computer Architecture, Verilog, Tcl, Python, Perl, Cadence Innovus, EDA Tools, digital logic, Physical Design, Methodology

Physical Design CAD

Tcl, Python, ECO timing closure, Timing Constraints, primetime, EDA Tools, Ir, Innovus, Sta, ICC2, Physical Design, Tempus, Seahawk, RTL2GDSII flow