static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

Cadence tool experience, jitter and signal equalization techniques, Phase Interpolator, layout and physical verification, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES

routing, Signal Integrity, CTS, floorplanning, Timing Closure, IR EM and variability analysis, Placement, low-power design, ASIC SOC physical design implementation, Physical Verification

Physical Design Verification, FinFet designs, Calibre, DRC, ESD coverage techniques, LVS, Physical Verification flow automation, DFM techniques, Siemens tools

layout and physical verification, jitter and signal equalization techniques, Phase Interpolator, CMOS design, High Speed Clock Distribution, Bias and Bandgap Voltage Regulators, Low jitter PLL, CAD tools for circuit simulation, SERDES