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Showing 3 jobs
Skills:
Vcs, System Verilog, JTAG protocols, Logic Equivalency checking, ATPG, Scan and BIST architectures, Gate level simulation debugging
Skills:
Vcs, Tcl, System Verilog, Python, Perl, TetraMax, Logic Equivalency checking, TestMax, EDA Tools, JTAG protocols, ATPG, Scan and BIST architectures, Tessent, primetime
Skills:
Vcs, System Verilog, JTAG protocols, ATPG, Logic Equivalency checking, Gate level simulation debugging, Scan and BIST architectures
