Verilog, Debugging, Windows, UNIX, System Verilog, Digital IP development, Automated flows for generating RTL

Unix, Shell, C, Perl, Linux, Verilog, Python, Uvm, systemverilog

Arm, C, Python, Perl, Uvm, vManager, RISC-V Assembly, Cadence SKILL, systemverilog, Mixed Signal chips

C, Shell, Verilog, Python, Test Planning, Tcl, Systemc, Transaction-level modeling using SystemVerilog, systemverilog, Assertions, Power-aware verification using UPF, Constrained-random verification, UVM-based testbench development, formal verification, NoC bus and interconnect verification

Debugging, System Verilog, Axi, CHI, Problem-solving skills, APB, ARM bus protocols, SoC system architecture, Uvm, AHB, Virtual Memory concepts

Svn, Version Control Systems, Python, Git, Perl, Tcl, cdc, CXL.mem architectures, CHI, CXL.cache, Mentor, Cadence, RDC, EDA Tools, Resets, Siemens, PCIe protocol architecture, Synthesis, Ace, Verilog RTL development, AMBA protocols, systemverilog, CXL.io, LINT, performance optimization, Synopsys