Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

Microsoft Hyper-v, BGP, C, Vmware Esxi, Gdb, Kvm, Wireshark, OSPF, Python, Qos, OpenStack, Go, qemu

C, Vcs, Perl, Verilog, cdc, Hardware Emulation Platforms, ASIC SoC development, systemverilog, Rtl Design, spyglass, EVE, ASIC Design, Veloce, formal verification

Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, Timing Analysis, Rtl Design, Eco, Debussy, bring-up lab debug

test mode timing constraints definition, DFTMax, Cadence Encounter Test, simulating test vectors, Transition delay test coverage analysis, ASIC DFT, Genus Synopsys, TetraMax, equivalence check DFT DRC rules, DFT concepts, timing fixes, Scan Insertion, ATPG coverage analysis

Sql, Shell scripting, Grafana, Linux, Lsf, Tcl, Python, Perl, Jenkins, Git, Synopsys VCS, EDA Tools, Mentor Calibre, Sungrid UGE, Cadence Virtuoso