Perl, Python, Tcl, Clock domain partitioning, Block and subsystem-level physical design flows, primetime, Power integrity and power-aware physical implementation, Clock gating, Fusion Compiler, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Golang, Google Cloud Platform, Python, Sql, GenAI models, Google BigQuery

Unix, Python, Lsf, Bitbucket, Static timing analysis, AI ML, Jenkins, Git, Linux, Splunk, GenAI, cdc, Design Verification, design layout constraints, CI CD process, DesignSync, UPF, SDC, Dft, RDC, EDA Tools, Graph Neural Networks, Implementation, make, reinforcement learning, debug tools, convolutional Networks, Power-aware flows, Clocks, SW development

Git, Pcie, Perl, Verilog, Shell scripting, Ethernet, Static Timing Analysis, System Verilog, Python, Tcl, Sta, LINT, cdc, AXI-based interconnects, Dft, Synthesis, RDC, CXL

Pcie, Perl, Python, System Verilog, Tcl, CHI, SMMU, assertion-based verification, Uvm, Coresight, Axi, coverage-driven testing, CXL, SVA

static timing analysis, Python, Genus Design Compiler, place-and-route Encounter Innovus ICC, high-speed SerDes, physical verification DRC LVS, 3DIC implementation methodologies, DFT methodologies, Asic Physical Design, Verilog RTL, Cadence Virtuoso, RTL Compiler, Clock Tree Synthesis, ASIC synthesis, scripting or programming languages