Meet the team

You'll be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts.

As part of our team, you'll contribute to the development of our next-generation network devices - Cisco Silicon One™. Our team operates in a startup-like environment within a stable and leading corporation.

Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.

We are revolutionizing the industry by building a new internet for the AI era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.

Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!

Your Impact

You'll be joining our CAD Physical Design teams within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Physical Synthesis, Place and Route, Optimization, Timing Closure, and other Signoff disciplines.

You will lead a CAD team within the PDM organization, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Minimum Qualifications

BSc/MSc in Electrical or Computer Engineering required with 10+ years of experience
Expertise in PnR and Signoff methodologies.
Proficiency with industry-standard tools.
Strong scripting experience in TCL, Python, and automation frameworks.
Experience with large-scale SoC programs.
Prior management experience

Preferred Qualifications

Familiarity with networking ASIC design challenges (e.g., low latency, high-throughput clocking, SerDes, packet processors) is a strong plus.
Excellent verbal and oral communication skills with ability to work independently across geographically distributed teams
Proven track record in leading and training junior team members
Prior experience in a large enterprise engineering organization or global silicon team is a plus.

Why Cisco

At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

CAD/Methodology Physical Design Team Lead

CAD/Methodology Physical Design Team Lead