Pcie, Vcs, System Verilog, Security IPs, Verdi, Ethernet interfaces, Axi, FPGA simulation tools, performance grading, MACSec, UVM flow development

Jtag, Perl, Verilog, Python, System Verilog, Tcl, Mentor Questa, Cadence Xcelium, JasperGold, Uvm, Synopsys VCS, APB, EDA Tools, CRI, IJTAG

Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms

System Verilog, Data path verification performance tests, Building test benches from scratch, Gate level simulation, ASIC verification using UVM

Jasper, Python Scripting, Verilog, System Verilog, formal verification, VC-FORMAL, SVA