Python Scripting, Git, ASIC design flow, RTL design in Verilog, Version control systems such as Perforce, ICManage, Modern SOC tools including Spyglass, ASIC design in sub-20nm technology nodes, PrimeTime or equivalent tools, Cadence Conformal, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, Questa CDC, VCS simulation

Tcl, Python Scripting, Perl, PrimeTime or equivalent tools, ASIC design flow, Low power digital design and analysis, ASIC design in sub-20nm technology nodes, Digital Design, C embedded experience, Circuit timing STA, RTL design in Verilog SystemVerilog

Python Scripting, PrimeTime or equivalent tools, ASIC design flow, ASIC design in sub-20nm technology nodes, Low power digital design and analysis, Digital Design, C embedded experience, Circuit timing STA, RTL design in Verilog SystemVerilog