Vcs, System Verilog, JTAG protocols, ATPG, Logic Equivalency checking, Gate level simulation debugging, Scan and BIST architectures

Vcs, Tcl, System Verilog, Python, Perl, TetraMax, Logic Equivalency checking, TestMax, EDA Tools, JTAG protocols, ATPG, Scan and BIST architectures, Tessent, primetime