boundary scan , Vcs, Python, Perl, Tcl, Scan Insertion, sdf debugging, DFT CAD development, Jtag protocols, DFT logic IP integration, p1687, p1500, EDA Tools, BIST architectures, Test static timing analysis, Tessent tool sets, Test Architecture Methodology, Infrastructure, memory BIST, TetraMax, Verilog design, Functional Verification, ATPG, Gate level simulation, Timing Closure, timing based simulations, TestMax

Vcs, System Verilog, primetime, JTAG protocols, Tessent, Logic Equivalency checking, ATPG, EDA Tools, TestMax, TetraMax, Scan and BIST architectures

Static Timing Analysis, System Verilog, DFT CAD development, JTAG protocols, Logic Equivalency checking, ATPG, Post-silicon validation, Test Architecture Methodology, Scan and BIST architectures, Verilog design