Verilog, System Verilog, assertion and coverage-driven verification, Synopsys VCS, Cadence IES, formal property checking tools, Uvm, SVA

Jasper, Pcie, Verilog, System Verilog, Synopsys VC-Formal Magellan, formal property checking tools, Uvm, Cadence IEV, Synopsys VCS, HBM, Cadence IES, SVA

Verilog, System Verilog, Jasper, Simulation Tools, Synopsys VCS, Synopsys VC-Formal Magellan, Uvm, Cadence IES, Cadence IEV, Formal property checking tools

C, Systemc, Makefile, Verilog, Ruby, System Verilog, Perl, Debugging firmware and RTL code using simulation tools, Graphics pipeline knowledge, Developing UVM based verification frameworks, UVM testbenches, Simulation profile efficiency improvement, TLM, IP-level ASIC verification