Sta, PG creation and push-down methodologies, Physical Verification, SoC RTL to GDSII implementation, Scripting flow deployment, RDL knowledge, SoC Full-chip floorplanning, Die file generation, Feed-through planning, Hierarchical design implementation, PnR implementation

shielding , custom layout design, signal flow optimization, isolation, device matching, LVS, Power Planning, layout architecture, IR optimization, clock routing, parasitic minimization, power routing, biasing, EDA Tools, ERC, DRC, Cadence Virtuoso, EM IR latch-up prevention, parasitic management, ESD protection

computational design , wiring diagrams , High Voltage (HV) transmission and distribution substations, Secondary systems electrical design, P&C schematics, Automation of data manipulation, P&C room layout, CAD documentation to UK Energy standards, Protection coordination, ETAP software, Design algorithms

data link layer , PCIe PHY-MAC interface protocols, Physical Layer, flow control, CDC synchronizers, SerDes PHY, async FIFO, integrating PCIe hard IP controller, PnR constraints, CXL 1.1 2.0 or 3.0 protocol knowledge, reset sequencing, Transaction Layer, multi-clock-domain design, wrapper RTL, error handling, SystemVerilog RTL, clock crossing, PCIe power management, PCI-SIG certification process, PCIe architecture, Virtual Channels, PCIe compliance testing, TLP structure

hierarchical layout techniques, 3nm technology, Mentor Graphics Calibre, custom layout design, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices

District Cooling Plants (DCP), Mechanical design calculations, Pump selection with head calculations, Hydraulic Institution ANSI HI standards, Surge analysis, NFPA, Pipework and valve sizing, Design of pumping stations, Hydraulic Institution HI, Piping and mechanical equipment layout arrangement, HVAC sizing, Lifting equipment and filter selection, AWWA

production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design

power converters , post layout parasitic extraction, Monte Carlo analysis, bandgaps, sensing circuitry, Simulation, block level topology selection, Spectre, switching regulators, schematic generation, DACs, VHDL, charge pumps, Amplifiers, physical layout management, Spice, Transistor Level Design, Comparators, IC CAD tools, analog and mixed signal design, precision analog control

RTL design verification, Verilog RTL development, Synthesis, Post silicon validation, Timing Closure, low power design, Design quality checks, Front-end EDA tools, Digital IP ASIC design