IP Program Management, timing validation, mixed signal IP design, PNR, test layout, analog logic design

Board Bring Up, Doors, Technical Documentation, Reports, Power Supply Design, antennas, chambers, EMI EMC qualification testing, Through Hole and SMD board assembly process, Power Electronics, PCB layout fabrication process, hardware design and development lifecycle process, DO-160, Procedures, EMI EMC instruments, qualification test plan, MIL-STD-461, DO-254 Process

low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

Shell, Perl, Analog Design Environment, Analog Design Flow, Virtuoso Schematic Editor, Virtuoso Layout Features

Unix, ESD protection schemes, Latch-up prevention, skill programming, Cadence Virtuoso Layout XL, layout dependent effects, Cadence Design environment, Calibre verification tools, P R methods, SKILLCAD

automation, LVS, tape-out procedures, BCD technologies, custom analog layout, foundry-specific constraints, internal layout flows, DRC

low power design, Timing Closure, Synthesis, Verilog RTL development, Front-end EDA tools, RTL design verification, Digital IP ASIC design, Post silicon validation, Design quality checks

Analog, Layout Design, Architecture, Circuit Designing, Mixed Signal, Packaging, Project Execution, Manager Technology, AMS Design