Logic Design, Static-timing closure, Verification, Debug skills, Synthesis, Front-end design tools and methodologies, Micro-architecture, Timing signoff, Gate-level simulations, Block-level function verification, RTL coding techniques, formal verification

cdc, RTL Coding, Synthesis, Rtl Design, DV debug, Debug, Dft, ip design

Uart, Test Plans, Pcie, coverage closure, CDC checks, LINT, timing closure verification, WiFi MAC architectures, IP enhancements, SDIO, functional coverage, WiFi 802.11 standard, RTL implementation, power analysis, Digital Design

Unix, Pyspark, Bash, Data Analytics, Sql, Shell, Linux, Perl, Ruby, Python, Electrical Engineering, Product Quality, Power Electronics, Failure Analysis, Embedded Systems, Power Systems, Reliability

Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Mentor, Cadence, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis

synopsys primetime , Synopsys FusionCompiler, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, AI ML Integration, Advanced Node Experience, Advanced Clocking

PERL, Python, Tcl, Ir, Cadence, Mentor, LVS, EM Signoff, Synthesis, Formal Equivalence, DRC, Synopsys