Systemc, Windows, Linux, Makefile, Shell, Verilog, Ruby, System Verilog, Perl, TLM, graphics pipeline knowledge, Simulation Tools, IP level ASIC verification, debugging firmware and RTL code, automating workflows, UVM testbenches, HLS tools, simulation profile efficiency improvement, UVM based verification frameworks

Tcl, Python, Perl, SV, SoC Verification, Uvm, Functional vectors generation, MBIST verification, SV UVM monitors, Test controller architecture, ATE Functional CHAZ vector enablement

Jtag, System Verilog, Python, Pcie, Perl, UVM methodology, High speed USB, UltraSoC, RISC Debug Architectures, Design for Debug, Tessent Embedded Analytics