Perl, Python, formal verification, property checking, RTL integration, Uvm, systemverilog

Systemc, Windows, Linux, Makefile, Shell, Verilog, Ruby, System Verilog, Perl, TLM, graphics pipeline knowledge, Simulation Tools, IP level ASIC verification, debugging firmware and RTL code, automating workflows, UVM testbenches, HLS tools, simulation profile efficiency improvement, UVM based verification frameworks

C++, Linux, Perl, Ruby, Makefile, Shell, UVM concepts, SystemVerilog language, HLS tools

C, Verilog, System Verilog, AI tools, SoC UPF power aware verification, Uvm, DFx DFT infrastructure functional verification

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

arm architecture , AI ML SoC exposure, Gate-Level Simulation, Cadence Tools, Arm Corestone, ATE pattern generation support, Test Bench Development, SystemVerilog UVM, ASIC SOC verification, Low-power verification experience, Functional Verification, AXI AHB APB Protocols

Jtag, Pcie, Perl, System Verilog, Python, Tessent Embedded Analytics, UltraSoC, UVM methodology, Design for Debug, High speed USB, RISC Debug Architectures

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools