hardware engineering , Digital Logic Design, Embedded Firmware, Scripting Languages, Jtag, Verilog, System Verilog, IEEE1500, Micro-processor debug, Power management verification, Memory dump, MBIST, UPF, Assertions, C Language, Scan dump, DFT architecture, formal verification

co-routines, Uvm, CVM, Verilator, multi-threaded programming

snoops, Coverage, SystemVerilog UVM assertions, ARM AMBA CHI, Ordering, caches, cache coherency concepts, MESI, SystemVerilog UVM, load store atomics, multicore CPU architectures, MOESI

C, Ovm, virtualization, Perl, Python, Tcl, Client Server centric CPU features, SystemVerilog Assertions, cache controllers, x86 assembly, semi randomized test generators, FPGA HW platforms, Uvm, systemverilog, Validation using Emulation, validation strategy development, memory coherency, debugging test failures, power management, coverage driven Validation methodologies