perl scripting, Jasper, Verilog, Computer Architecture, System Verilog, VSI-FV, digital systems, assembly x86 code, IEV, IFV, CPU verification, Formal Verification methodology

perl scripting, Jasper, Verilog, Computer Architecture, System Verilog, VSI-FV, digital systems, assembly x86 code, IEV, IFV, CPU verification, Formal Verification methodology

System Verilog, Pcie, Protocol analyzers, Bring up tools, Uvm, Verification and validation flows, Oscilloscopes

Python Scripting, System Verilog, SOC design, AXI Protocol, SoC Verification, UVM Testbench

Ovm, Pcie, Verilog, Ethernet, System Verilog, power management flows, Uvm, HSIO, Low Power Verification, RTL GLS level simulations, SOC bot flow, System Verilog Assertions

Debugging, System Verilog, Axi, Problem-solving skills, CHI, ARM bus protocols, APB, SoC system architecture, Uvm, AHB, Virtual Memory concepts

Verilog, System Design, Automation

Tcl, System Verilog, Python, Perl, RTL Coding, Uvm, Simulation