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Senior RTL design engineer - SOC Intergration

AMD Ventures
Hyderabad, India

Skills:

Python Scripting, PrimeTime or equivalent tools, ASIC design flow, ASIC design in sub-20nm technology nodes, Low power digital design and analysis, Digital Design, C embedded experience, Circuit timing STA, RTL design in Verilog SystemVerilog

Early Applicant

Senior RTL design engineer - SOC Intergration

Xilinx
X
Hyderabad, India

Skills:

Tcl, Python Scripting, Perl, PrimeTime or equivalent tools, ASIC design flow, Low power digital design and analysis, ASIC design in sub-20nm technology nodes, Digital Design, C embedded experience, Circuit timing STA, RTL design in Verilog SystemVerilog

Early Applicant
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