Logic Design, Static-timing closure, Verification, Debug skills, Synthesis, Front-end design tools and methodologies, Micro-architecture, Timing signoff, Gate-level simulations, Block-level function verification, RTL coding techniques, formal verification

cdc, RTL Coding, Synthesis, Rtl Design, DV debug, Debug, Dft, ip design

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi