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ASIC DFT Engineering Technical Leader | Scan, ATPG, MBIST

Sell Cisco
Bengaluru, India

Skills:

boundary scan , Vcs, Perl, Python, Tcl, sdf debugging, Scan Insertion, Jtag protocols, memory BIST, TetraMax, Verilog design, p1687, p1500, ATPG, Gate level simulation, EDA Tools, Timing Closure, BIST architectures, Test static timing analysis, Tessent tool sets, timing based simulations, TestMax

Early Applicant

ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years

Cisco Live
Bengaluru, India

Skills:

System Verilog, Post-silicon validation, Test Architecture Methodology and Infrastructure, Test Static Timing Analysis, DFT CAD development, Logic Equivalency checking, JTAG protocols, ATPG, Scan and BIST architectures

Early Applicant

ASIC Engineering Technical Lead :: DFT/MBIST/ATPG/Scan Insertion :: Exp 12+ Years

Cisco Home
Bengaluru, India

Skills:

Static Timing Analysis, System Verilog, DFT CAD development, JTAG protocols, Logic Equivalency checking, ATPG, Post-silicon validation, Test Architecture Methodology, Scan and BIST architectures, Verilog design

Early Applicant
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