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We are seeking a motivated DFx engineer to join our CDFX team. In this role, you will contribute to the next generation of AMD's silicon innovation while developing your expertise in DFx methodologies and advanced design practices. You will be part of a forward-thinking engineering organization that values learning, encourages fresh ideas, and empowers emerging talent to grow into impactful contributors who help shape the future of semiconductor technology.

Key Responsibilities

The successful candidate will own/lead the DFX Design Architect, Develop and implement cutting edge DFX features including SCAN, ATPG, MBIST, BSCAN, etc. Work closely with the DFX Architecture and the various IP Design teams to align on the DFX requirements and successfully implement the DFX design Design and develop correct by construction DFX design and support DFX verification Work closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects. Work with the Synthesis and PD team to ensure correct DFT implementation in Scan/ATPG.

Preferred Experience

Experience and understanding of ASIC DFX, Scan synthesis, Integration flow using Fusion Compiler, ATPG experience in tile and SoC level experience. Applicant should be familiar with scan hardware compressions, failure mechanisms and debug processes.

Familiar in ICl Extraction, SSN, IJTAG,EDT, TestKompress, simulation and verification flow and experience of working in DFX architecture of complex SOC. Implement and deploy automated design flows to implement DFT features in a complex SOC ASIC design or IP subsystem Experience in End-to-End DFX flow development/creation. DC/AC scan (at-speed) development, debug and test. Expert in at least one of the scripting tool (Perl, Python, TCL) and ability to create complex flows/scripts that provide scalable solutions to DFX implementation.

Strong EDA tools experience Tessent - Testkompress, SSN, IJTAG, Synopsys - Fusion compiler, Design Compiler, Spyglass Experience with RTL quality check tools/methodologies such as Spyglass, Lint is required. Exposure to Static timing analysis & Timing closure is required. Scan/ATPG patterns & test flows development, debug, test, and characterization Excellent hands-on debug skills and scripting skills are critical. Strong communication skills and the ability to collaborate effectively within a global team environment are essential.

Strong problem-solving skills Knowledge & experience of low power concepts, clock gating, power gating is a plus

ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering how it integrates into SoC.

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

This posting is for an existing vacancy.

DFT - SCAN/ATPG Lead Engineer