Windows, C, Systemc, Usb, Linux, Verilog, Makefile, Shell, Ruby, System Verilog, Ethernet, Perl, Pcie, Graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, AXI ACE Protocols, UVM testbenches, HLS tools, TLM, simulation profile efficiency improvement, UVM based verification frameworks

simvision , Hspice, Verdi, Xcellium, Finseim, Analog Mixed Signal Verification, Spice, MS RVM model writing, verilog a, Mixed signal Digital simulations, Verisium, Verilog Models, virtuoso, Waveview, primesim