PERL, Verilog, Tcl, Uvm, systemverilog

Makefile, Windows, Perl, Linux, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, testbenches, Efficiency Improvement, UVM-based verification frameworks

Makefile, Windows, Perl, Linux, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, UVM-based verification frameworks