Jasper, Verilog, System Verilog, Cadence IEV, Synopsys VCS, Synopsys VC-Formal Magellan, Cadence IES, Formal property checking tools, Uvm, Simulation Tools

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP-level ASIC verification, graphics pipeline knowledge, acceleration HLS tools, RTL code, Simulation Tools, UVM testbenches, automating workflows, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware, testbenches processes and flows

Windows, C, Systemc, Usb, Linux, Verilog, Makefile, Ruby, System Verilog, Ethernet, Perl, Pcie, Graphics pipeline knowledge, debugging firmware and RTL code using simulation tools, IP level ASIC verification, AXI ACE Protocols, UVM testbenches, TLM, simulation profile efficiency improvement, UVM based verification frameworks

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools