Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our we affectionately refer to it as the and it's won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo we did not achieve record revenue and over without a great team dedicated to empowering innovation. People like you.

Visit our page to see what exciting opportunities and company await!

Job Description:

Potentially take ownership of early-stage backend design tasks for assigned blocks, including DFT RTL hookup, RTL QA (structural and design rule checks), SDC (timing constraints) creation and review, power estimation, and signoff checklist management.
Perform synthesis and identify and address design issues early.
Implement Design-For-Test (DFT) on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) which are coded in VHDL/Verilog.
Perform physical design flows, Place & Route and close timing on very large and complex ASICs and SOCs in Very-Deep Sub-Micron (VDSM) process technology nodes.
Potentially work on multiple blocks in parallel.
Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones.
Collaborate with RTL designers, physical design, implementation and DFT teams to ensure early detection and resolution of issues related to RTL, synthesis, constraints, floorplans and timing.
Communicate regularly with the local project lead to resolve issues and to ensure meeting targeted goals and
schedule.
Document lessons learned, process improvements, and recommendations for future projects.
Proactively identify opportunities to improve efficiency, parallelize work, and offload engineers.
Communicate clearly and effectively with global teams (including regular online meetings and written updates).

About the AES Automation Team

The AES Automation Team is part of Microchip's Advanced Engineering Services (AES) organization, focused on flow improvement, technical advising, and driving PPA and TTM across digital design and physical implementation teams. We partner closely with product design and CAD groups to deliver best-in-class silicon solutions.

Requirements/Qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
Understanding of digital design, including RTL (SystemVerilog), synthesis, SDC.
Understand logic timing requirement (setup/hold/uncertainties)
Strong scripting skills (Python, TCL and shell).
Excellent communication skills, with the ability to collaborate across time zones and cultures.
Able to work independently, debug issues and solve problems.
Willingness to take ownership and deliver results.

Preferred Qualifications

Experience with EDA tools such as Genus, Conformal LEC/CLP, Joules, Fishtail, Innovus, Tempus, Pegasus, Redhawk or similar.
Experience with flow/process development/debug/support, or shift-left methodologies.
Familiarity with DFT, and logic equivalence checking (LEC).
Familiarity with power estimation with vectors, and UPF (unified power format).
2 years of ASIC develop experience.

Engineer II – Design