Vcs, Static Timing Analysis, Scan Insertion, Post-silicon validation, P1687, TetraMax, ATE patterns, JTAG protocols, ATPG, Gate level simulation, Tessent tool sets, TestMax

Vcs, Perl, System Verilog, Python, Tcl, primetime, Logic Equivalency checking, TetraMax, Scan and BIST architectures, JTAG protocols, Tessent, ATPG, EDA Tools, TestMax