Jasper, Pcie, Verilog, System Verilog, Synopsys VC-Formal Magellan, formal property checking tools, Uvm, Cadence IEV, Synopsys VCS, HBM, Cadence IES, SVA

Systemc, C, Windows, Linux, Verilog, Makefile, Ruby, System Verilog, Perl, graphics pipeline knowledge, debugging firmware and RTL code, automating workflows, HLS tools, UVM testbenches, TLM, simulation profile efficiency improvement, UVM based verification frameworks, IP-level ASIC verification

C, Systemc, Makefile, Verilog, Ruby, System Verilog, Perl, Debugging firmware and RTL code using simulation tools, Graphics pipeline knowledge, Developing UVM based verification frameworks, UVM testbenches, Simulation profile efficiency improvement, TLM, IP-level ASIC verification