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Showing 8 jobs
Skills:
redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking
Skills:
routing, block level place and route, floor-planning, Power grid analysis, Extraction, Physical Synthesis, Netlist, full chip implementation, GDS flow, STA timing, flow-automation, Signal Integrity, clock tree optimization, formal verification, Dft, Timing Constraints, Regression, digital design automation, Timing Closure, CTS IO timing, RTL-to-GDSII, Antenna fixing
Skills:
Tcl, Python, PERL, Seahawk, Tempus, primetime, Innovus, ICC2
Skills:
Scripting, Physical Verification, Physical Design, PG creation, ESD latch-up, RDL knowledge, Innovus, floorplanning
Skills:
Static Timing analysis, Perl, Tcl, Clock Planning, SoC designs, Power Plan, Digital place and route, Floor Planning, Clock Tree Synthesis, Parasitic Extraction, PnR Signoff
Skills:
Physical Design CAD
Skills:
Floorplan convergence, Electrical, low power designs, scripting with TCL, automations
Skills:
System Engineering, Physical Design, Analog Design
