C, DDR, Perl, System Verilog, Python, Tcl, AMBA protocols, Uvm, Axi, HBM, APB, LPDDR, AHB

hardware engineering , Digital Logic Design, Embedded Firmware, Scripting Languages, Jtag, Verilog, System Verilog, IEEE1500, Micro-processor debug, Power management verification, Memory dump, MBIST, UPF, Assertions, C Language, Scan dump, DFT architecture, formal verification

System Verilog, Building test benches from scratch, ASIC verification using UVM

Perl, Verilog, Python, Synopsys VCS, Cadence Incisive, formal verification, VHDL, Modelsim, Uvm

Vcs, Jenkins, Git, Pcie, Ethernet, Python, System Verilog, Tcl, Xcelium, SERDES, Uvm, GitLab CI, formal verification, Questa

System Verilog, low-power design verification, Uvm