Pcie, Perl, Ethernet, Python, System Verilog, Axi, APB, RoCE, CXL, AMBA protocols, Uvm

simvision , Tcl, C, Vcs, Shell, Python, Questa, Uvm, systemverilog, Xcelium, Verdi, functional coverage, regression management, constrained-random verification, DVE

Ml, Tcl, Python, Perl, regression management, simulation coverage analysis, AMS Co-Simulation, Uvm, mixed-signal verification, systemverilog, Ai

Pcie, Ovm, Debugging, Unix Shell Scripting, Verilog, System Verilog, Perl, Tcl Scripting, DDR, Circuit Analysis, Uvm, IC chip design development flow process, CAE CAD tools, Circuit Design, test bench development, VHDL, AHB, Axi, CMOS logic design, coverage assertion driven verification, CMOS device operation and characteristics, verification plans, Simulation