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Showing 2 jobs
Skills:
Vcs, Static Timing Analysis, Scan Insertion, Post-silicon validation, P1687, TetraMax, ATE patterns, JTAG protocols, Gate level simulation, ATPG, Tessent tool sets, TestMax
Skills:
Vcs, System Verilog, JTAG protocols, ATPG, Logic Equivalency checking, Gate level simulation debugging, Scan and BIST architectures
