Verilog, System Verilog, Scripting Languages, asynchronous design concepts, Synthesis, LINT, SoC design flows, RTL integration, Sta, Rtl Design, power analysis, Digital Design, CDC methodologies

Shell, Tcl, Perl, DMA, digital design fundamentals, control data path logic, protocol bridges, low-power design flows, systemverilog, power performance and area optimization techniques, lint CDC RDC synthesis STA constraints, RTL design using Verilog, memory-mapped peripherals, micro-architecture definition, Dft, bus fabrics, debugging skills for simulation synthesis and integration issues

Soc, Static Timing Analysis, Digital Circuits