System Verilog, Python, Tcl, RTL synthesis tool development, UPF, parallel algorithms, formal verification, Dft, VHDL, RTL gate level logic optimizations, RTL synthesis technology, RTL design IP development, power synthesis, logic optimizations, Dynamic Power

Devops, Cloud Technologies, Vmware Esxi, Virtualization, Linux Systems, Troubleshooting

Devops, Cloud Technologies, Vmware Esxi, Virtualization, Linux Systems, Customer Support, Troubleshooting

sdk development , Ip Routing, Lag, Distributed Systems, Qos, Debugging, Python Programming, Q-in-Q, Problem Solving, LACPD, Mac-Learning, Ethernet-OAM, HAL layer for Broadcom Marvell chips

Perl, Verilog, Python, SV, Cadence or equivalent simulation tools, SV scripting languages

Java, C, CSS, HTML, Sql, ELT, Nosql, Javascript, Socket Programming, Networking Protocols, Restful Apis, Python, Etl, Go, Microservices architecture, Vector datastores