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Showing 5 jobs
Skills:
Perl, Python, Tcl, VPlan, Synopsys VCS, Synopsys VC Formal, JasperGold, Cadence simulation tools, AMBA protocols, Uvm, systemverilog
Skills:
C, Pcie, Ethernet, SV, CXL, Uvm, UCIe, systemverilog
Skills:
liberty , boundary scan , Svn, JIRA, DDR, Jtag, Pcie, Verilog, Scripting, System Verilog, Tcl, python, PHY-level IO interfaces, bump map pattern definition, pad ring planning, RTL, IO standards, lef, SERDES, EDA Tools, IEEE 1149.1, IO library cells, Isp, Orbit IO, DFT methodologies, flow automation, IO cell placement, CXL
Skills:
C, Perl, Verilog, Shell scripting, Python, Tcl, SVA, UVM assertions, systemverilog
Skills:
Python, Tcl, Shell scripting, Debugging, Perl, Uvm, systemverilog, Mixed-Signal Verification
