C, testbenches, Emulation, Simulation, RTL, Digital Design, CPU verification, Uvm, coverage models

cdc, Dft, Synthesis, DV debug, Debug, RTL Coding, Rtl Design, ip design

C, Linux, Pcie, SAS, Sata, Windows, Python, NAND memory operation, bus analyzers, digital oscilloscopes, logic analyzers

C, Shell, Verilog, Python, Test Planning, Tcl, Systemc, Transaction-level modeling using SystemVerilog, systemverilog, Assertions, Power-aware verification using UPF, Constrained-random verification, UVM-based testbench development, formal verification, NoC bus and interconnect verification

Logic Design, Perl, Python, Tcl, Sta, MBIST OCC validation flows, Mentor, Cadence, Physical design flows, SpyGlass DFT rules, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, Digital Circuit Design, SSN design and IEEE 1687 IJTAG standards, Synopsys, RTL design synthesis