C, Emulation, Simulation, RTL, Digital Design, CPU verification, Uvm

synopsys primetime , Tcl Scripting, Timing exceptions, SDC constraints, Design Compiler, OCV, Constraint debugging, Skew, Latency, PVT corner analysis, Setup hold timing, Clock definitions, Timing derates, Signal integrity effects, Synthesis optimization, RTL-to-gate synthesis, POCV, PPA trade-offs, Root-cause resolution, Clock uncertainty, AOCV, Timing-driven mapping, MMMC analysis

Perl, Bash, Python, Tcl, C, shell scripting, simulation and emulation environments, verification methodologies, Linux Unix environment, SystemVerilog UVM, test plan creation and execution

regulators , temperature sensors , Dll, Reference Circuits, PMU circuits, RC Oscillators, Validation, Mixed-Signal Design, Crystal Oscillators, Analog design and simulation tools, Switching Regulators, Pll, Signal Chains, Oscillator, Precision Comparators, Analog IC Design, characterization, Debug, Silicon bring-up

C, Pcie, Ethernet, SV, CXL, UCIe, Uvm, systemverilog

Uncore subsystems, Physical Design, FinFET nodes, EDA suites, Cadence, Synopsys, RTL-to-GDSII

nand flash , automation, Garbage Collection, Debugging, C Programming, Log Analysis, digital hardware design, SSD flash translation layer, AI-assisted engineering tools for firmware development, test generation, SSD Storage Firmware Development, Firmware design and debug, Wear leveling, SLC MLC QLC concepts