C, Uart, Spi, Shell, Verilog, Ethernet, I2c, Python, Systemc, Tcl, SVI3, systemverilog, Axi, formal verification, DMA, UVM-based testbench development, AHB, power-aware verification UPF, NoC bus and interconnect verification

static timing analysis, Dft, low-power design methodologies, LINT, Cadence-based ASIC design environments, micro-architecture development, SystemVerilog RTL design, formal verification, Logic Synthesis, cdc

Debugging test pattern issues, Scan Insertion, DFT implementation, Programming or scripting, ATPG, DFT RTL insertion, SRAM repair, MBIST, DFT methodology, LBIST

static timing analysis, Perl, Python, EDA tools for synthesis, LINT, cdc, RTL design using Verilog, Simulation, RTL quality tools such as Spyglass, RDC, VHDL, low-power design techniques, digital IC ASIC design

Verilog, Computer Architecture, Subsystem hardening, Synthesis, object-oriented programming, floorplanning, Place And Route, DFT insertion, digital logic, VHDL, RTL-to-GDSII implementation, EDA Tools, Timing Closure, Clock Tree Synthesis

code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

System Verilog, design and verification methodologies, VHDL, packet processing architectures, block level verification using SV UVM Python or C, Digital Design, low-power design techniques, CMOS logic

Jtag, System Verilog, Static timing analysis, DFT techniques, IEEE 1500 Standard, Commercial test generation tools, Logic diagnosis, Yield learning, Synopsys DFT Max, Tetramax tools, Verification UVM methodology, Mentor Tessent, IEEE 1687 standard, ATPG test pattern translation, ATPG tools, Scan insertion tools, Chip design Verilog, MBIST, Familiarity with ATE, Scripting Perl, Scan compression, Test compression software, Gate-level simulations, LBIST