synopsys primetime , Perl, Python, Tweaker, Power-Aware Verification UPF, Cadence CCD, Sign-off STA Synopsys PrimeTime PT PT-PX, Cadence Conformal LEC, PrimeClosure, Cadence Tempus, Synopsys Formality, Formal Verification LEC, Constraints Validation Synopsys TCM GCA Ausdia TimeVision SpyGlass, Timing Closure ECO Cadence Tempus

Dft, Tessent Modus MBIST, Scan Compression, SCAN pattern simulations, MBIST, Tessent Modus diagnosis tool, Tessent Modus ATPG, Scan Stitching, JTAG Techniques

Dft, Tessent Modus MBIST, Scan Compression, SCAN pattern simulations, MBIST, Tessent Modus diagnosis tool, Scan Stitching, Tessent Modus ATPG, JTAG Techniques

High-speed digital design, Switching fabric design, High-bandwidth data movement architectures, High-speed interconnects, Memory subsystem design, Low-power methodologies, Debugging and performance analysis, SoC architecture and integration, Synthesis, Microcontroller-based systems, ASIC development flows, Silicon bring-up

System Verilog, Synthesis, microarchitecture specification, Complex Control Logic, Lint closure, Post-Silicon Debug, Timing Constraints, Networking ASICs, Designing Fabric Network On Chip, RTL coding in Verilog, Digital Design

automation, Scripting, Static Timing Analysis, Python, AHB, Synthesis, LINT, EDA Tools, frontend flows, memory interfaces, standard interface protocols, SoC-level integration, cdc, Memory Controller IPs, Rtl Design, Safety Security and Debug architectures, Interconnect Fabrics, formal verification techniques, static dynamic power checks, Axi, Dft, ARM Cores

Timing Analysis, Logic Synthesis, Verilog Coding, Digital IC design methodologies, ASIC design flows