conformal lec , Clp, Perl, Python, Tcl, Fusion Compiler, Formality, LEC, MCMM methodologies, UPF, Cadence Genus, Synthesis, Synopsys Design Compiler, RTL-to-GDS, CPF, Low Power Verification

Dft, Tessent Modus MBIST, Scan Compression, SCAN pattern simulations, MBIST, Tessent Modus diagnosis tool, Scan Stitching, Tessent Modus ATPG, JTAG Techniques

Pcie, Verilog, Ethernet, Synthesis, cdc, UALink, Simulation, timing considerations, UCIe, systemverilog, LINT, CXL

UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), C, C++, Shell, Pcie, Perl, Arm, Python, Tcl, Systemc, MCU, Hardware Emulation Platforms, RISC-V, UCIe, systemverilog, Verification Methodology, AMBA, Axi, Formal Model Equivalence Checking Tools, formal verification, VC Formal

clocking , Verilog, EDA tools for synthesis, LINT, Use of AI for design, cdc, SoC-level design and integration, Synthesis flows, Rtl Design, spyglass, VHDL, Verification methodologies, RDC, Digital design principles, Resets, Timing Constraints, Micro-architecture design, Low-power design techniques, Timing Analysis