Verilog, Cache, Soc Architecture, fabric coherence, memory compression, systemverilog, logic synthesis techniques, FPGA and emulation platforms, digital logic design principles, Synthesis, DRAM, FPGA design verification, assertion-based formal verification, RTL design concepts, Dft, low-power design techniques, power analysis

Usb, Fpga, Perl, Pcie, Python, verification methodologies, coverage driven verification, Emulation, directed constrained-random tests, Uvm, systemverilog, formal verification, MIPI, AMBA, Test Bench, transaction level modeling, AXI4

arm architecture , Git, Gerrit, Embedded C Programming, Bare-metal programming, Boot-time software, Embedded Systems, SoC subsystems

Debugging Tools, Pcie, Ethernet, DSP algorithms, clock validation, memory subsystems, fuse controllers, verification methodologies, Simulation Tools, AMBA protocols, IP Subsystem SoC-level verification, microarchitecture concepts, systemverilog, coverage closure, boot flows, security validation flows, random test case development, debugging capabilities for SoC fabric, advanced computer architecture, Performance Analysis

code coverage , perl, C, Regression Testing, Ovm, Pcie, Ethernet, Python, Uvm, systemverilog, Axi, DDR protocols, RTL simulators, X-propagation, functional coverage

DDR, Usb, C, Pcie, Uart, I2c, Spi, Object-Oriented Programming, I3C, Uvm, systemverilog

Embedded C, Fpga, C, Spi, DDR, Pcie, Sata, Usb, Uefi, BIOS, Pci, System Architecture, emulation verification, Post Silicon Validation, Memory subsystem, technical debug, Security Protocols, NPU, power management, emulation platforms, SoC IP level Power Management, Validation, low power design, validation strategy, high speed IO, MIPI, Axi, SoC Verification