boundary scan , Perl, Python, Sta, Scan Insertion, SDC constraints, MBIST, Physical design flows, Verification, SpyGlass DFT rules, ATPG pattern generation, Hierarchical DFT, RTL design synthesis

test mode timing constraints definition, Genus Synopsys, DFT concepts, Scan Insertion, Transition delay test coverage analysis, TetraMax, equivalence check DFT DRC rules, simulating test vectors, ATPG coverage analysis, Cadence Encounter Test, DFTMax, ASIC DFT, timing fixes

Jtag, Dft, MBIST, Design Engineer

Perl, Verilog, Python, Tcl, Pre-Silicon test planning, low power concepts, RTL design for DFT, MBIST, DFT methodologies, systemverilog, Siemens Mentor Tessent, DFT Compiler, ATPG, Synopsys TetraMAX, DFT Integration Verification, Scan, Memory Repair, IJTAG

C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, gate-level simulation, DFT micro-architecture, Timing Constraints, EDA Tools, Synopsys Tetramax, Scan, Mentor Tessent