Jtag, System Verilog, Static timing analysis, DFT techniques, IEEE 1500 Standard, Commercial test generation tools, Logic diagnosis, Yield learning, Synopsys DFT Max, Tetramax tools, Verification UVM methodology, Mentor Tessent, IEEE 1687 standard, ATPG test pattern translation, ATPG tools, Scan insertion tools, Chip design Verilog, MBIST, Familiarity with ATE, Scripting Perl, Scan compression, Test compression software, Gate-level simulations, LBIST

DFT - Scan insertion and architecture, DFT Compiler, Mentor Graphics Tessent, Cadence Modus, ATPG, Synopsys TestMAX, Test Compression