DDR, Pcie, Debugging, System Verilog, verification methodologies, Uvm, NAND, ASIC simulation tools

C, Requirements Traceability, Test Plan Creation, Tcl, Verilog, System Verilog, Python, Perl, Microprocessor architecture, interconnect, Assertions, UVM methodology, Gate Level Simulation, Testcase creation, Directed and constrained random methodologies, Metric Driven Verification, Coverage closure, Formal verification methodologies, SoC Verification, Functional and code coverage