static timing analysis, Verilog, Synthesis, Simulation, formal verification tools, multi-power-domain design techniques, Uvm, systemverilog, Synopsys Spyglass, VHDL, Siemens Questa Formal, digital design flow, FPGA design methodologies

power optimization , Verification Methodologies, Mixed-Signal Integration, Timing Closure, Digital Circuit Design, Digital Architecture

Fpga, Verilog, System Verilog, I2c, Simulation Tools, Digital Design, cdc, RTL Coding, Memory Architecture, audio signal chain, Cadence, VHDL, TDM, LINT, constraint development, Synthesis, ASI, digital timing analysis, RDC

Protocol knowledge (DDR, MIPI), Scripting (C/C++, Python), Pcie, Tcl, Perl, Micro-architecture design, SystemVerilog and Verilog coding, UVM/VMM/OVM verification methodologies, AMBA, Synthesis and static timing analysis

Physical Design, Vlsi, digital circuit design

Shell, PERL, System Verilog, Python, Tcl, digital IC circuit design, full-chip mixed-signal verification, HDL synthesis, digital design verification, Uvm

static timing analysis, Python, Perl, RDC, LINT, digital IC ASIC design, RTL quality tools such as Spyglass, cdc, RTL design using Verilog, VHDL, EDA tools for synthesis, low-power design techniques, Simulation