Ant, Mentor Calibre, floorplanning, high speed GHz circuit design, LVS, 7nm and below CMOS process geometries, Latch-up, signal and clock shielding, EMIR, layout design for mixed analog digital ICs, high performance data converters, Esd, ERC, DRC, isolation techniques, signal flow planning, Cadence Virtuoso, Reliability

Ant, EMIR, Reliability, high speed GHz circuit design, CMOS process geometries, LVS, floorplanning, Memory analog layout design, layout design for mixed analog digital ICs, Mentor Calibre, Esd, signal flow planning, ERC, Cadence Virtuoso, DRC, isolation techniques, high performance data converters, Latch-up, signal and clock shielding

Parasitic effects, LVS DRC PEX EMIR verification flows, xACT, Reference circuits, Calibre DRC, Bandgap Oscillators, StarRC