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Showing 2 jobs
Skills:
C, Vcs, Jtag, Perl, Verilog, Python, Tcl, Verdi, MBIST, gate-level simulation, DFT micro-architecture, Timing Constraints, EDA Tools, Synopsys Tetramax, Scan, Mentor Tessent
Skills:
Perl, Verilog, Python, Tcl, Pre-Silicon test planning, low power concepts, RTL design for DFT, MBIST, DFT methodologies, systemverilog, Siemens Mentor Tessent, DFT Compiler, ATPG, Synopsys TetraMAX, DFT Integration Verification, Scan, Memory Repair, IJTAG
