redhawk , Python, Routing, Perl, Tcl, OCV, Signoff, CTS, Fusion Compiler, advanced packaging technologies, ICC2, SDC development, Tempus, hierarchical STA, SI Crosstalk, StarRC, POCV, Placement, UPF Low-Power, floorplanning, CRPR, MCMM timing closure, AOCV, ECO timing closure

logic bist , Usb, Perl, Pcie, Shell scripting, Static Timing Analysis, Python, Tcl, Memory BIST, Mentor, Cadence, IEEE 1149.1 JTAG, IEEE 1500, Analog Mixed-Signal test structures, DFT architecture, ATPG, EDA Tools, IEEE 1687 IJTAG, Siemens, Synopsys

FEA tools, Debugging, Control loop theory, PCB CAD tools, power management, Circuit Design, Board level analog and digital circuit design, Data analysis using Excel or JMP, PCB schematic design, Troubleshooting

PERL, Python, Tcl, Sta, RTL-GDS flows, Physical Verification, SNPS CAD Flow, SNPS CDNS-based tools

Logic Design, Synopsys, MBIST OCC validation flows, IEEE 1687 IJTAG standards, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Mentor, Sta, Cadence, DFT for complex ASIC SoC designs, SSN design, Physical design flows, RTL design synthesis

bist , Perl, Debugging, Python, Tcl, Logic Design, Sta, RTL, Scan, make, tessent, on-chip scan compression, gate level simulation, Fault Models, automation methods, ATPG, pattern generation, VLSI simulation tools, Fault Simulation

scripting skills in Perl, tessent DFT, DFT architecture definition, HDLs, Genus, Scan, MBIST, Cadence digital implementation tools, Tempus, JTAG boundary scan, ATPG flow implementation

bist , boundary scan , Jtag, Soc, Tcl, Python, Shell Scripting, Silicon Validation, Dft, Design for Test, Scan Insertion, Scan Compression, ATPG, MBIST, LBIST, IJTAG, IEEE 1149.1, IEEE 1500, IEEE 1687, TestMAX, DFT Compiler, TetraMax, Tessent, Cadence Modus, occ, EDT, RTL, ASIC, Semiconductor, Vlsi