IP Program Management, timing validation, mixed signal IP design, design for test, Layout, PNR, analog logic design

Debugging, Clp, Silicon Validation, Dft, Scan Insertion, ATPG, Rtl Design, Timing Closure, LEC, IEEE 1500

production yield targets, transistor-level design, block-level modeling, SPICE Spectre simulation, mixed-signal IC design for mobile applications, advanced packaging, top-level simulation, IC physical layout management, Cadence CAD toolset, BCD process technologies, analog mixed-signal IC design, VHDL co-simulation, system-level verification, semiconductor IC processing, hand analysis, production test solutions, IC system partitioning, top-down IC design methodologies, signal chain analysis, architectural trade-off analysis

Scripting Languages, Sta, Synthesis, Flow development, PNR, Digital Implementation flow, debugging skills, ML based Solutions

Logic Design, Static Timing Analysis, Tcl, Python, Perl, Jasper, IR drop, coverage analysis, RTL lint tools, ATE debug, Logic Synthesis, EDA Tools, Sta, RTL2GDS flow, Logic Equivalent Checking, Cadence Modus, Synthesis, post silicon validation, Verification, DFT concepts, ATPG tools, RTL implementation, debugging skills, Scan Insertion

Logic Design, DDR, HBM technologies, Tx Rx CTLE Amplifiers Samplers, system level design, AMS verification, Lab debugs on AMS IPs, Analog Mixed Signal design, High-speed circuits, AMS design techniques, Mixed Signal IP design, Circuit architecture, SERDES