Python Scripting, Verilog, Logic schematic analysis, gate level simulations, Spice, AI-assisted tools, Timing Analysis

C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

C, Makefile, Windows, Shell, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, acceleration HLS tools process, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools

Usb, DDR, Pcie, Verilog, UVM based Verification IP development, Scripting for automation, Uvm, systemverilog, AMBA AXI, APB, AHB, System Verilog Assertions